A goal in the fabrication of gallium arsenide power MESFETs is minimizing the gate length. Minimizing the gate length yields the benefit of faster device operation. However, prior art methods for minimizing the gate length are limited by the resolution limits of lithography methods or did not provide a method for forming the optimal gate recess for power MESFETs. In addition, an integrated circuit designer when laying out a MESFET must allow a specific buffer region between the source, the gate and the drain in order to avoid overlap between these respective regions. FIG. 1 is a side view schematic diagram of a partially formed MESFET formed using techniques known in the art. Source region 21 and drain region 22 are formed in substrate 20. Photoresist layer 23 is patterned to provide an opening 27 for forming the gate of MESFET 26. Width 24 is the smallest opening capable of being patterned using the photolithographic technique used to pattern photoresist layer 23. Widths 25 are the deviation tolerances and are included to insure that the gate formed using photoresist layer 23 does not make contact with either source region 21 or drain region 22 and thus short the gate to the drain. Thus the narrowest gate length which may be fabricated using this prior art technique is width 24. In addition, this prior art method for forming a MESFET can only form a transistor having a minimum gate width of width 24 plus two width 25s.
Because of this limitation, it is an object of the invention to provide a method for forming an MESFET, which includes a gate having a length shorter than the smallest opening which may be patterned using a given lithographic system. One technique for providing patterned openings smaller than those possible using lithographic techniques alone is the use of shadow deposition. Shadow deposition involves depositing a masking material at an angle over a vertical extension on the surface of the integrated circuit. The vertical extension blocks the deposition of masking material below the point where the vertical extension is interposed in the path of the deposited material, thereby providing a mask which has an opening which is the "shadow" of the vertical extension. However, prior art shadow deposition techniques do not provide a method for forming a gate and gate recess of the proper proportions for power MESFETs (i.e. having the same length).